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| MC100LVEL13 3.3V ECL Dual 1:3 Fanout Buffer Description The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer. The Low Output-Output Skew of the device makes it ideal for distributing two different frequency synchronous signals. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE, The D input will bias around VCC/2 and the Q output will go LOW. Features http://onsemi.com * * * * * * * * * * * * * Pb-Free Packages are Available* 500 ps Typical Propagation Delays 50 ps Output-Output Skews ESD Protection: >2 kV Human Body Model The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V Internal Input Pulldown Resistors Q Output will Default LOW with Inputs Open or at VEE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 143 devices SO-20 WB DW SUFFIX CASE 751D MARKING DIAGRAM* 20 100LVEL13 AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2006 November, 2006 - Rev. 5 1 Publication Order Number: MC100LVEL13/D MC100LVEL13 Q1a Q1a Q2a Q2a VCC Q2b Q2b Q1b Q1b 20 19 18 17 16 15 14 13 12 VEE 11 Table 1. PIN DESCRIPTION PIN Qna, Qna Qnb, Qnb CLKn, CLKn VCC VEE FUNCTION ECL Differential Clock Outputs ECL Differential Clock Outputs ECL Differential Clock Inputs Positive Supply Negative Supply 1 2 3 4 5 6 7 8 9 10 Q0a Q0a VCC CLKa CLKa CLKb CLKb VCC Q0b Q0b Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View) Table 2. MAXIMUM RATINGS Symbol VCC VEE VI Iout TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C <2 to 3 sec @ 260C 20 SOIC 20 SOIC 20 SOIC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 to 0 -8 to 0 6 to 0 -6 to 0 50 100 -40 to +85 -65 to +150 90 60 30 to 35 265 265 Unit V V V V mA mA C C C/W C/W C/W C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 MC100LVEL13 Table 3. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 1) -40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 6) VPP < 500 mV VPP y 500 mV Input HIGH Current Input LOW Current CLKn CLKn 0.5 -300 2215 1470 2135 1490 Min Typ 30 2295 1605 Max 38 2420 1745 2420 1825 2275 1490 2135 1490 Min 25C Typ 30 2345 1595 Max 38 2420 1680 2420 1825 2275 1490 2135 1490 Min 85C Typ 32 2345 1595 Max 40 2420 1680 2420 1825 Unit mA mV mV mV mV 1.3 1.5 2.9 2.9 150 1.2 1.4 2.9 2.9 150 1.2 1.4 2.9 2.9 150 V V mA mA mA IIH IIL 0.5 -300 0.5 -300 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 4. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = -3.3 V (Note 4) -40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 5) Output LOW Voltage (Note 5) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 6) VPP < 500 mV VPP y 500 mV Input HIGH Current Input LOW Current CLKn CLKn 0.5 -300 -1085 -1830 -1165 -1810 Min Typ 30 -1005 -1695 Max 38 -880 -1555 -880 -1475 -1025 -1810 -1165 -1810 Min 25C Typ 30 -955 -1705 Max 38 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 Min 85C Typ 32 -955 -1705 Max 40 -880 -1620 -880 -1475 Unit mA mV mV mV mV -2.0 -1.8 -0.4 -0.4 150 -2.1 -1.9 -0.4 -0.4 150 -2.1 -1.9 -0.4 -0.4 150 V V mA mA mA IIH IIL 0.5 -300 0.5 -300 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 5. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. http://onsemi.com 3 MC100LVEL13 Table 5. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -3.3 V (Note 7) -40C Symbol fmax tPLH tPHL tsk(O) Characteristic Maximum Toggle Frequency Propagation Delay CLK to Q/Q Output-Output Skew Any Qa to Qa, Any Qb to Qb Any Qa to Any Qb Duty Cycle Skew |tPLH-tPHL| Cycle-to-Cycle Jitter Input Swing (Note 8) Output Rise/Fall Times Q (20% - 80%) 150 230 TBD 1000 500 150 230 410 Min Typ TBD 600 430 Max Min 25C Typ TBD 500 620 450 Max Min 85C Typ TBD 640 Max Unit GHz ps ps 50 75 50 TBD 50 75 50 TBD 1000 500 150 230 50 75 50 tskew tJITTER VPP tr tf ps ps 1000 500 mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. VEE can vary 0.3 V. 8. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40. Q Driver Device Q Zo = 50 W D Receiver Device Zo = 50 W 50 W 50 W D VTT VTT = VCC - 2.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) http://onsemi.com 4 MC100LVEL13 ORDERING INFORMATION Device MC100LVEL13DW MC100LVEL13DWG MC100LVEL13DWR2 MC100LVEL13DWR2G Package SO-20 WB SO-20 WB (Pb-Free) SO-20 WB SO-20 WB (Pb-Free) Shipping 38 Units / Rail 38 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices http://onsemi.com 5 MC100LVEL13 PACKAGE DIMENSIONS SO-20 WB DW SUFFIX CASE 751D-05 ISSUE G D A 11 X 45 _ q NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ H M B M 20 10X 0.25 E 1 10 20X B 0.25 M B TA S B S A e SEATING PLANE h 18X A1 T C ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative L http://onsemi.com 6 MC100LVEL13/D |
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